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| INTEGRATED CIRCUITS DATA SHEET SAA7708H Car Radio Digital Signal Processor Preliminary specification File under Integrated Circuits, RACE/docu/7708N1A_Datasht.frm 1998 May 19 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor CONTENTS 1 2 3 4 5 6 7 8 9 9.1 10 10.1 10.1.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.3 10.4 10.5 10.6 10.7 10.7.1 10.7.2 10.7.3 10.7.4 10.7.5 10.7.6 10.7.7 10.7.8 10.7.9 10.7.10 10.7.11 10.7.12 10.8 10.8.1 10.8.2 10.8.3 10.8.4 10.8.5 10.8.6 10.8.7 10.8.8 10.9 GENERAL DESCRIPTION HARDWARE FEATURES SOFTWARE FEATURES APPLICATIONS QUICK REFERENCE DATA ORDERING INFORMATION APPLICATION BLOCK DIAGRAM BLOCK DIAGRAM PINNING Pinning diagram FUNCTIONAL DESCRIPTION Signal path for Level information The VREFAD pin Signal path of the third order switched capacitor AD's. The FM MPX signal path Input sensitivity for FM and RDS The signal flow of the AM, CD analog and TAPE Analog source switching The realisation of common mode inputs Phone input with volume control Input selection switches Supply of the analog inputs The DCS clock block Synchronization with the DSP core IAC General description Parameter setting for the MPX input ignition detector AGC set point (1 bit) Threshold sensitivity offset (3 bits) Deviation feed forward factor (3 bits) Suppresion stretch time (3 bits) MPX delay Level IAC threshold (4 bits) Level IAC feed forward setting (2 bits) Level IAC suppression stretch time (2 bits) Dynamic IAC threshold levels IAC testing Analog outputs D/A converters Upsample filter Volume control Function of the POM pin The Fader Power off plop suppression The Internal VREFDA pin Supply of the analog outputs Clock circuit and oscillator SAA7708H 1998 May 19 2 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.9.1 10.10 10.11 10.12 10.13 10.14 10.14.1 10.14.2 10.14.3 10.14.4 10.14.4.1 10.14.4.2 10.14.4.3 10.15 10.15.1 10.15.2 10.15.3 10.15.4 10.16 10.17 11 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 19.5 20 20.1 20.2 20.3 20.4 20.5 20.6 20.7 21 22 Supply of the X-tal oscillator The phase lock loop circuit to generate the DSP and other clocks The DSP core DSP core status register and the external control pins I2C control (SCL and SDA pin) I2S and SPDIF inputs General description I2S inputs The timing diagram of the communication is shown in Fig. 11. Digital data stream formats General description SPDIF INPUTS SPDIF format SPDIF channel modulation Timing Characteristicse logic. RDS decoder (RDS_CLOCK / RDS_DATA pins) Clock and data recovery Timing of Clock and Data signals Buffering of RDS data Buffer interface DSP Reset Power supply connection and EMC ELECTRICAL CHARACTERISTICS THERMAL RESISTANCE DC CHARACTERISTICS ANALOG INPUTS ANALOG OUTPUTS OSCILLATOR RDS TIMING SUPPLY CURRENTS I2C BUS CONTROL AND COMMANDS Characteristics of the I2C Bus Bit transfer Start and stop conditions Data transfer Acknowledge I2C BUS FORMAT Addressing Slave address (A0 pin) CDSP write cycles CDSP READ cycles I2C memory map specification I2C Memory map definition Table definitions APPLICATION DIAGRAM MECHANICAL OUTLINE DRAWING OF PACKAGE SAA7708H 1998 May 19 3 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 1 GENERAL DESCRIPTION SAA7708H The CDSP-chip performs all the signal functions in front of the power amplifiers and behind the AM and FM_MPX demodulation of a car radio or the tape input. These functions are: interference absorption, stereo decoding, RDS decoding, FM and AM weak signal processing (soft-mute, sliding stereo, etc.), Dolby-B tape noise reduction and the audio controls (volume, balance, fader and tone). Some functions have been implemented in hardware (stereo decoder, RDS decoding and IAC for FM_MPX) and are not freely programmable. A digital audio signals from external sources with the Philips I2S and the LSB 16, 18 and 20 bit justified format or SPDIF format are accepted. There are four independent analog output channels.. The DSP contains a basic program which enables a set with AM/FM reception, sophisticated FM weak signal functions, MSS, Dolby-B tape noise reduction system, CD play with compressor function and separate bass and treble tone control and fader/balance control. 2 HARDWARE FEATURES * Two 3rd order SCAD (switch cap analog to digital converters) * D/A converters with four fold over sampling and noise shaping * Digital stereo decoder for the FM_MPX signal * Improved, digital IAC for FM * RDS processing with optional 16 bit buffer via a separate channel. * Phone input with common mode rejection. Can be mixed with DAC output of front channels or processed via an AD * Auxiliary high CMRR analog CD input (CD-walkman, speech, economic CD-changer etc.) * One separate full I2S and LSB justified format and two muxable SPDIF high performance input interfaces * Audio output short circuit protected * I2C bus controlled * AM input or AM_Right and AM_Left input * Phase Lock Loop to generate the high frequency DSP clock from common fundamental oscillator crystal * Combined AM/FM level input * Two analog single ended tape inputs * -40 to +85 C operating temperature range 3 SOFTWARE FEATURES * Improved FM weak signal processing * Integrated 19 kHz MPX filter and de-emphasis * Electronic adjustments: FM/AM level, FM channel separation, Dolby level * Baseband Audio processing (treble/bass/balance/fader/volume) * Dynamic loudness or bass boost * Audio level meter * Music Search detection for Tape (MSS) * Dolby-B tape noise reduction * CD dynamics compressor * CD De-emphasis processing * Improved AM processing with IAC * Soft Audio Mute 1998 May 19 4 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor * Extended Bleep functions * Pause detection for RDS updates * Signal level, noise and multipath detection for AM/FM signal quality information 4 APPLICATIONS SAA7708H * Car radio systems 1998 May 19 5 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 5 QUICK REFERENCE DATA SYMBOL Vd3 Vd5 IP3 IP5 IPA Ptot ADSNR ADICL AITHDM PARAMETER Operating supply voltage 3.3 Volt analog and digital CONDITIONS with respect to Vss all parts 3 4.5 48 0 1 kHz 1.1 Vrms, BW= 19 kHz, I2C default setting MIN TYP 3.3 5 57.4 5 16.5 0.273 54 -70 0.03 80 83 SAA7708H MAX 3.6 5.5 78 7 22.6 0.423 VDDA1 -65 0.056 V V UNIT Operating supply voltage 5 with respect to Vss all Volt periphery parts DC supply current of the 3.3 digital core part DC supply current of the 5V digital periphery part DC supply current of the analog part Total power dissipation Level AD converter SNR RMS (unweighted) Input voltage range level AD for full scale THD FM_MPX input high activity of the DSP at 31 MHz DSP frequency Without external load to ground At zero input and output signal high activity of the DSP at 31 MHz DSP frequency BW=0-29 kHz Max. input mA mA mA W dB V dB % dB AISNRM SNR FM_MPX input mono 1 kHz, BW=19 kHz, 0 dB ref. = 1.1 Vrms, I2C default setting SNR FM_MPX input stereo 1 kHz, BW=40 kHz, 0 dB ref. = 1.1 Vrms, I2C default setting THD CD Inputs, not multiplex mode SNR CD Input, not multiplex mode THD AM mono input, not multiplex SNR AM mono input, not multiplex THD Tape input, multiplex mode SNR Tape input, multiplex mode conversion input level DAC total harmonic distortion + noise vs Output Signal DAC DAC Dynamic Range 1 kHz, 0.55Vrms, BW=20 kHz 1 kHz, BW=20 kHz, 0 dB ref.= 0.55 Vrms 1 kHz, 0.55 Vrms, BW=5 kHz AISNRSS 74 77 - dB AITHDC - -80 0.01 -76 0.016 -76 0.016 -76 0.016 -65 dB % dB dB % dB dB % dB Vrms dBA AISNRC AITHDA 81 - 84 -80 0.01 88 -80 0.01 AISNRA AITHDT 1 kHz, BW=5 kHz, 0dB ref. 83 = 0.55 Vrms 1 kHz, BW = 20 kHz, 0.55 Vrms 1 kHz, BW= 20 kHz, 0 dB ref. = 0.55 Vrms THD < 1% Rload AC> 5 k, f=1 kHz 70 0.6 - AISNRT AILVL THD&N/S 77 0.66 -75 DRAN f = 1 kHz, -60 dB 92 102 - dBA 1998 May 19 6 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H SYMBOL DSIL XTFREQ DSPFREQ 6 PARAMETER DAC Digital Silence X-tal frequency Clock Frequency DSP core CONDITIONS f=20 Hz-17 kHz Aweighted MIN -102 TYP -108 11.2896 31.0464 - MAX UNIT dBA MHz MHz ORDERING INFORMATION EXTENDED TYPE NUMBER SAA7708H 80 PACKAGE PINS PIN POSITION QFP MATERIAL plastic CODE SOT318D4C 1998 May 19 7 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 7 APPLICATION BLOCK DIAGRAM SAA7708H RR POWER LF AMP RF Fig. 1 General application diagram LR SPDIF-1 SPDIF-2 CD_D (I2S) CD_A TAPE PHONE SAA7708H AM FM RDS Level AM/FM-IF AM/FM-RF 1998 May 19 AM/FM 8 TEA 6811 TEA6824 I2C RDS P Display 8 1998 May 19 BLOCK DIAGRAM Philips Semiconductors SAA7708H Phone Volume PHONE PH_GND CMRR stage LEVEL Signal Quality Front Left DAC Rear Left DSP Front Right DAC Rear Right ADC IAC ADC Stereo decoder ADC Signal Level Car Radio Digital Signal Processor CD_L CD_R CD_GND CMRR stage AM/AM_R AM_L 9 TAPE_L TAPE_R Analog Source Selector FM_MPX FM_RDS SEL_FR RDS decoder SPDIF I2S XTAL osc I2C Fig. 2 Simple block diagram Preliminary specification SAA7708H Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 9 9.1 PINNING Pinning diagram SAA7708H DSP_OUT1 DSP_IN2 DSP_IN1 VSSD5V2 VDDD5V2 TP12 TP11 TP10 TP9 TP8 TP7 CD_CL CD_DATA CD_WS TP6 SPDIF1 41 40 25 24 SPDIF2 VSSD5V1 VDDD5V1 TP5 TP4 TP3 TP2 TP1 FLV FLI FRI FRV VREFDA VDDA2 VSSA2 RLV RLI RRI RRV POM AUX_GND LEVEL VDACN1 VDACP DSP_OUT2 DSP_RESET RTCB SHTCB TSCAN VDDD5V3 VSSD5V3 VDDD3V1 VSSD3V1 VSSD3V2 VDDD3V2 VDDD3V3 VSSD3V3 VSSD3V4 VDDD3V4 A0 SCL SDA RDS_CLOCK RDS_DATA SEL_FR VSS_OSC OSC_IN OSC_OUT SAA7708H 64 65 1998 May 19 VDD_OSC AM/AM_R AM_L TAPE_R TAPE_L CD_RI PHONE CD_LI PHONE_GND VDDA1 VSSA1 VDACN2 CD_GND VREFAD FM_RDS FM_MPX Fig. 3 Pinning diagram. 10 80 1 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor Pinning Table Pin list SAA7708 SYMBOL PIN DESCRIPTION SAA7708H PIN TYPE VDACP VDACN1 LEVEL 1 2 3 Positive reference voltage SCAD1, SCAD2 and Level AD Ground reference voltage 1 SCAD1, SCAD2 and Level AD FM/AM-level input pin. Via this pin the level of the FM signal or level of the AM signal is fed to the CDSP. The level information is used in the DSP for signal correction By I2C switchable common mode reference pin to enable an arbitrary high common mode analog input. Power on Mute of the FADER DAC. Timing is determined by an external capacitor. Rear Right audio voltage output of the FADER DAC Rear Right audio current output of the FADER DAC Rear Left audio current output of the FADER DAC Rear Left audio voltage output of the FADER DAC Ground supply analog part of the FADER DAC and SPDIF bitslicer 3V positive supply analog part of the FADER DAC and SPDIF bitslicer Voltage reference of the analog part of the FADER DAC Front Right audio voltage output of the FADER DAC Front Right audio current output of the FADER DAC Front Left audio current output of the FADER DAC Front Left audio voltage output of the FADER DAC Test pin, may not be connected in the application Test pin, may not be connected in the application Test pin, may not be connected in the application Test pin, may not be connected in the application Test pin, may not be connected in the application 5V positive supply 1 peripheral cells only Ground supply 1 of 5 volt peripheral cells only Analog bitslicer input2 for SPDIF, can be selected i.s.o. SPDIF1 via I2C bit Analog bitslicer input1 for SPDIF, can be selected i.s.o. SPDIF2 via I2C bit Test pin, may not be connected in the application I2S or LSB justified format Word select input from a digital audio source I2S or LSB justified format Left-Right Data input from a digital audio source I2S Clock or LSB justified format input from a digital audio source Test pin, may not be connected in the application Test pin, may not be connected in the application Test pin, may not be connected in the application AP2D AP2D AP2D AUX_GND POM RRV RRI RLI RLV VSSA2 VDDA2 VREFDA FRV FRI FLI FLV TP1 TP2 TP3 TP4 TP5 VDDD5V1 VSSD5V1 SPDIF2 SPDIF1 TP6 CD_WS CD_DATA CD_CL TP7 TP8 TP9 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AP2D APR2D AP2D APR2D APR2D AP2D APVSS APVDD AP2D AP2D APR2D APR2D AP2D BT4CR BT4CR BT4CR BT4CR BD4CR VDDE5 VSSE5 APR2D APR2D SCHMITCD SCHMITCD SCHMITCD SCHMITCD BD4CRD SCHMITCD SCHMITCD 1998 May 19 11 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H SYMBOL PIN DESCRIPTION PIN TYPE TP10 TP11 TP12 VDDD5V2 VSSD5V2 DSP-IN1 DSP-IN2 DSP-OUT1 DSP-OUT2 DSP-RESET RTCB SHTCB TSCAN VDDD5V3 VSSD5V3 VDDD3V1 VSSD3V1 VSSD3V2 VDDD3V2 VDDD3V3 VSSD3V3 VSSD3V4 VDDD3V4 A0 SCL SDA RDS_CLOCK RDS_DATA SEL_FR 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Test pin, may not be connected in the application Test pin, may not be connected in the application Test pin, may not be connected in the application 5V positive supply 2 peripheral cells only Ground supply 2 of 5 volt peripheral cells only Digital input 1 of the DSP-core (F0 of the status register). Level must always be defined externally in the application. Digital input 2 of the DSP-core (F1 of the status register). Level must always be defined externally in the application. Digital output 1 of the DSP-core (F2 of the status register) Digital output 2 of the DSP-core (F3 of the status register) Reset of the DSP core (active low) Asynchronous Reset Test Control Block active low, connect to ground Shift Clock Test Control Block, connect to ground Scan control active high, connect to ground 5V positive supply 3 peripheral cells only Ground supply 3 of 5 volt peripheral cells only 3V positive supply 1 core only Ground supply 1 of 3 volt core only Ground supply 2 of 3 volt core only 3V positive supply 2 core only 3V positive supply 3 core only Ground supply 3 of 3 volt core only Ground supply 4 of 3 volt core only 3V positive supply 4 core only Slave sub-address I2C selection / Serial data input test control block Serial clock input I2C bus Serial data input / output I2C bus Radio Data System bit clock output / RDS external clock input Radio Data System data output AD input selection switch to enable high ohmic FM_MPX input at fast tuner search on FM_RDS input. At switch to `1' the input of the FM_RDS is put through to the MPX input of the dowsample filters and FM_MPX inputs gets high ohmic. Level must always be defined externally in the application. Ground supply crystal oscillator circuit Crystal oscillator input: crystal oscillator sense for gain control or forced input in slave mode Crystal oscillator output: Drive output to 11.2896 MHz crystal 3V positive supply crystal oscillator circuit BD4CRD BD4CRD SCHMITCD VDDE VSSE SCHMITC SCHMITC B4CR B4CR IBUFU SCHMITCD SCHMITCD SCHMITCD VDDE5 VSSE5 VDDI3 VSSI3 VSSI VDDI3 VDDI3 VSSI3 VSSI3 VDDI3 SCHMITCD SCHMITC BD4SCI4 BD4CR B4CR SCHMITC VSS_OSC OSC_IN OSC_OUT VDD_OSC 62 63 64 65 APVSS APR2D AP2D APVDD 1998 May 19 12 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H SYMBOL PIN DESCRIPTION PIN TYPE AM/AM_R AM_L TAPE_R TAPE_L CD_RI PHONE CD_LI PHONE_GND VDDA1 VSSA1 VDACN2 CD_GND VREFAD FM_RDS FM_MPX Table 1 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Analog input pin for AM audio frequency Right Channel or AM mono inputl Analog input pin for AM audio frequency Left Channel Input of the analog TAPE Right signal Input of the analog TAPE Left signal Input of the analog CD Right signal Input of common mode phone signal Input of the analog CD Left signal The common mode reference pin of the phone signal Positive supply analog SCAD1, SCAD2 and Level AD. Ground supply analog SCAD1, SCAD2 and Level AD. Ground reference voltage 2 SCAD1, SCAD2 and Level AD The common mode reference pin of the CD_AD LEFT and CD_AD RIGHT block Common mode reference voltage SCAD1, SCAD2 and Level AD Analog input pin for FM RDS signal Analog input pin for FM-Multiplex signal AP2D AP2D AP2D AP2D AP2D AP2D AP2D AP2D APVDD APVSS AP2D AP2D AP2D AP2D AP2D Brief explanation of used pin types EXPLANATION Analog IO (Input/Output) Analog IO with series resistor and clamp device Analog SUPPLY Analog GROUND 5 Volt Peripheral only supply ring 5 Volt Peripheral only gound connection, no connection to substrate 3.3 Volt SUPPLY to digital core and internal IO pads 3.3 Volt GROUND to digital core and internal IO pads, no substrate connection 3.3 Volt GROUND to digital core and internal IO pads with substrate connection CMOS Schmitt trigger input CMOS, Schmitt trigger input with active pull-down to VSSE5 CMOS, active pull-down to VSSE5 CMOS, active pull-up to VDDE5 Bidirectional CMOS IO buffer, 4 mA, slew rate control Bidirectional CMOS IO buffer, 4 mA, slew rate control, active pull down to VSSE5 4mA CMOS tristate ouput buffer, slew rate control 4mA CMOS ouput buffer, slew rate control CMOS IO pad with open drain output PIN TYPE AP2D APR2D APVDD APVSS VDDE5 VSSE5 VDDI3 VSSI3 VSSI SCHMITC SCHMITCD IBUFD IBUFU BD4CR BD4CRD BT4CR B4CR BD4SCI4 1998 May 19 13 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10 FUNCTIONAL DESCRIPTION 10.1 Signal path for Level information SAA7708H For FM weak signal processing, for AM and FM purposes (absolute level and multipath) a FM/AM Level input is implemented (pin LEVEL). In the case of radio reception the clocking of the filters and the AD is based on a 38 kHz Fs frequency. A DC input signal is converted by a bitstream first order Sigma-Delta AD converter followed by a decimation filter. The input signal has to be obtained from a radio part. The tuner must deliver the level information of either AM or FM to the LEVEL pin. 10.1.1 THE VREFAD PIN Via this pin the Midref voltage of the AD's is filtered. This Midref voltage is used as reference of the LEVEL AD and half supply reference of the two third order switch capacitor ADs. External capacitors (connected to VSSA1) prevents crosstalk between the AD's. This pin must also used in the application as reference for the inputs AM/AM_R, AM_L, , TAPE_L and TAPE_R (see Fig. 21). 10.2 10.2.1 Signal path of the third order switched capacitor AD's. THE FM MPX SIGNAL PATH The CDSP has in total three analog audio source channels. One of the analog inputs is the FM_MPX signal. Selection of this signal is achieved according Table 3. The multiplex FM signal is converted to the digital domain in SCAD1, a bitstream third order switched capacitor AD converter. A decimation filter reduces the output of the AD to a lower sample rate. From this filter the following signals are derived and are processed in the DSP. The outputs from this signal path to the DSP which are all running on a sample frequency of 38 kHz are: * Pilot presence indication: Pilot-I. This one bit signal is low for a pilot frequency deviation < 3 kHz and high for a pilot frequency deviation > 3 kHz AND the FM MPX stereodecoder is locked on a pilot tone. * `Left' and `Right' FM reception stereo signal: This is the 18 bit output of the stereo decoder after the matrix decoding in ISN I2S format.This signal is fed via a muxer to a general I2S interface block that communicates with the DSP. * A noise level information. This signal is derived from the first MPX decimation fiter via a wide band noise filter. Detection is done with an envelope detector. This noise level is filtered in the DSP core and is used to optimize the FM weak signal processing. Normally the FM_MPX input and the FM_RDS input have the same source. If the FM input contains a stereo radio channel, the pilot information is used to lock the clocking of the decimation filters of FM MPX and RDS path and also the stereo decoder. 10.2.2 INPUT SENSITIVITY FOR FM AND RDS The FM and RDS input sensitivity is designed for tuner front ends which deliver an output voltage of 200 mVrms at a modulation depth of 22.5 kHz of a 1 kHz tone. In this case the I2C bit pcs_ad_sel must be `o' and the SEL_FR switch is also low. The MPX part of the FM_MPX signal will be processed via SCAD1, the RDS part is processed via SCAD2.. Another input sensitivity can be obtained by putting the pcs_ad_sel bit high. Biasing of this input must now take place exterenally via high-ohmic resistors connected to the VREFAD pin. In this case the input sensitivity has increased from 200 mVrms to 65 mVrms at modulation depth of 22.5 kHz. Reduction of the input sensitivity can be obtained by an external resistor tap consisting of an in the signal path placed series resistor and a resistor to VREFAD. 10.2.3 THE SIGNAL FLOW OF THE AM, CD ANALOG AND TAPE The signal AM mono via the AM/AM_R input can be selected by the correct values of the I2C bits. There is also an option available to connect a left and right signal to the chip. This can be for instance the AM-Right and AM-Left signal. The AM, TAPE and CD inputs are buffered by an opamp to ensure a high ohmic input that makes external signal reduction 1998 May 19 14 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H possible via an external resistor divider. For correct biasing of the first input buffer it is obligatory to connect the resistor between the tap and the virtual ground of the VREFAD pin (see Fig. 28). The way to make a high common mode input is described in chapter 10.2.5. 1998 May 19 15 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.2.4 ANALOG SOURCE SWITCHING SAA7708H INPUT SELECTOR ROUTER VOLUME PHONE SCAD1 SCAD2 Level AD PHONE_GND AUX_GND AM/AM_R FM_MPX CD_GND AM_L TAPE_L FM_RDS LEVEL PHONE CONTROL STAGE CMRR GAIN TAPE_R Fig. 4 Analog input switching circuit 1998 May 19 16 SEL_FR CD_RI CD_LI Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.2.5 THE REALISATION OF COMMON MODE INPUTS SAA7708H A high Common Mode Rejection Ratio can be created by the use of the either the AUX_GND or the CD_GND pin. One of these pins can be connected via the switches s10 and s11 (see Fig. 5) to the plus input of the second opamp in the signal path of TAPE, CD or AM. The signal of which a high common mode rejection ratio is required has one signal (or two signals) and a common signal as input. The common signal is connected to either the AUX_GND or CD_GND input and for the specific mode selected with the switches 10 and 11. This means that on both signal lines going to the SCAD will contain the common mode signal. The AD's itself will suppress this common mode signal very effectively and this is the way good common mode signal suppression is achieved. The switches needed are drawn in the appropriate position. The inputs CD_LI and CD_RI get in this example a diminished input signal by the external resistor tap of 8k2 and 10k. The 10k resistors provides together with the 1 M resistor from CD_GND to VREFAD also the biasing of the opamps OA1 and OA2. If no external resistor tap is needed still resistors will be needed between the signal inputs and the CD_GND pin. The CD_GND pin is in this configuration connected to the plus input of the opamps OA3 and OA4. Biasing of the opamps OA3 and OA4 is again provided by the 1 M resistor to VREFAD. In this construction the common mode signals on CD_LI / CD_RI and the CD_GND pin will be unchanged in amplitude being present at the AD input and the common mode rejection behaviour of these AD will provide a good common mode rejection ratio. The other common mode input AUX_GND can in the same way be used. CD PLAYER 8k2 LEFT CD_LI s1 s4 10k 10k OA1 10k TO SCAD1 TO SCAD1 10k CD_GND GROUND CD PLAYER CABLE CD PLAYER RIGHT CD_RI 10k 8k2 s2 s5 1M s10 s11 OA3 VREFAD 10k 10k OA2 10k TO SCAD2 or SCAD1 TO SCAD2 or SCAD1 OA4 OFF CHIP ON CHIP Fig. 5 Example of the use of common mode analog input 1998 May 19 17 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.2.6 PHONE INPUT WITH VOLUME CONTROL SAA7708H TO AD p0 PHONE PHONE_GND R 0.4R p1 Midref (VREFAD) Phone common mode stage R 2R p3 2R 2R p4 R TO AD 2R p2 Rd FL_b FL_b Rd FL_V DAC VREFDA Rd FR_b FR_b Rd FR_V FL_b FR_b DAC Phone current adding at DAC Fig. 6 Volume control setting of PHONE input A common mode input with volume control for mixing to the Front Left or Front Right or both DAC outputs is provided. The inputs consist of a PHONE input for the signal and a PHONE_GND to be connected to the ground shield of the PHONE cable. By means of two opamps the signal is then converted to a signal with better common mode rejection ratio. Via the switches s6_7 and the multiplex switch in front of the SCAD1 this signal can be processed via the AD signal path. In that case the resistor volume control must be put in an all `00000' position of the I2C bits p4-p0 meaning 0 dB pass through mode (see Fig. 6). Although in this way signal improvement with the DSP can be done, mixing with other analog sources is not possible. Another signal path is the R 2R volume setting block to the DAC current input. The signal from the phone opamp is converted via a R-2R ladder network to a voltage. This voltage can be controlled with the I2C bits p4,p3,p2,p1,p0 according Table 2. This voltage can be connected to two resistors in the DAC block via the I2C controlled switches FL_b and FR_b. The two resistors convert the voltage to a current an this current is added to the already present current of the Front Left DA and/or the Front Right DA. This is the way the phone signal is mixed with the DAC signal in the analog domain. 1998 May 19 18 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor Table 2 Volume settings of the PHONE input ($0FFE) FL AND FR OUTPUT (DB) 0 -3 -6 -9 -12 -15 -18 -21 MUTE Input selection switches SAA7708H VOL_PHONE BITS P4,P3,P2,P1,P0 00000 00001 00010 00011 00110 01110 01111 01111 1111* 10.3 In Fig. 4 a block diagram of the input is shown. The input selection is controlled by bits in the input selector control register and the input pin SEL_FR. The relation between these bits and the switches is indicated in table 3. This table is not 100% elaborated but gives an idea of the switching possibilities. Table 3 Analog input selection via I2Cbits ($0FFD) signal destination MODE FM_MPX + RDS mode 200 mV FM_MPX + RDS mode 65 mV AM mono + RDS AM stereo + RDS TAPE STEREO + RDS CD-ANALOG + RDS CD ANALOG PHONE via SCAD1 + RDS pcs_ad _sel 0 en_38 _clk 0 sw_ ad1 0 rds_cd _sel 0 s1_2 d s4_5 d s6_7 d s8_9 0 wide_ narrow 0 1 0 0 0 d d d 0 0 0 or 1 0 or 1 0 or 1 0 1 1 0 d d 0 0 0 0 0 1 1 1 0 d 0 0 1 1 1 0 0 0 0 or 1 d 0 or 1 1 0 0 d 1 1 0 1 0 0 0 d 0 0 d 0 0 1 1 d d 0 1 0 * In all the positions above one supposes that the SEL_FR pin is low. The switches s10 and s11 must be switched according the position needed for the correct common mode rejection ratio of the chosen input e.g. s10=0 and s11=1 in case of CD analog input. 1998 May 19 19 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.4 Supply of the analog inputs SAA7708H The analog input circuit has separate power supply connections to allow maximum filtering. These pins are the VSSA1 for the analog ground and the VDDA1 for the analog power supply. 10.5 The DCS clock block For the digital stereo decoder a clock signal is needed which is the 512 multiple of the pilot tone frequency of the FM MPX signal. This is done by the DCS clock block, which generates this 512 * 19 kHz = 9.728 MHz clock, the DCS clock, by locking to the pilot frequency. This block is also able to generate other frequencies and controlling is done via a number of I2C bits of the registers in Table 21 and Table 22. Default I2C settings of the DCS and the PLL guarantee correct functioning of the DCS block. 10.6 Synchronization with the DSP core The system can run in case of I2S input on different audio sample frequencies of Fs=32kHz, 38 kHz, 44.1 kHz or 48 kHz. After each processing period of one input sample with this signal, the Input flag (I-flag) of the status register of the DSP core is set on the falling edge of the I2S WS to I=1 during 4 clock cycles. This flag can be tested with a conditional branch instruction in the DSP. This synchronisation starts really in parallel with the input signal due to the short period that the I flag is set. It is obvious that the higher the Fs the lower the number of cycles available in the DSP program.. 10.7 10.7.1 IAC GENERAL DESCRIPTION The Interference Absorption Circuit (IAC) detects and suppresses ignition interference. This hardware IAC is a modified, digitized and extended version of the analog circuit which is in use for many years already. The IAC consists of an MPX mute function switched by mute pulses from ignition interference pulse detectors. All IAC functions must be switched off if there is no FM MPX signal processing. The input signal of a first IAC detection circuit is the output signal of ADF1. This interference detector analyses the high frequency contents of the MPX signal. The discrimination between interference pulses and other signals is performed by a special Philips patented fuzzy logic like algorithm and is based on probability calculations. This detector performs optimally in higher antenna voltage circumstances. On detection of ignition interference, this logic will send appropriate pulses to the MPX mute switch. The input signal of a second IAC detection circuit is the LEVEL signal (the output of the Level AD). This detector performs optimally in lower antenna voltage circumstances. It is therefore complementary to the first detector. The characteristics of both IAC detectors can be adapted to the properties of different FM front ends by means of the predefined coefficients in the IAC control registers. The values can be changed via the I2C bus. Both IAC detectors can be switched on or off independently of each other. Both IAC detectors can mute the MPX signal independently of each other. A third IAC function is the Dynamic IAC circuit. This block is intended to switch off the IAC completely the moment the MPX signal has a too high frequency deviation which in case of narrow IF filters can result in AM modulation. This AM modulation could be interpreted by the IAC circuitry as interference caused by the car's engine. AM IAC is also implemented. In this case only the AM mono signal is monitored by the on the DSP processor running program. Input from the LEVEL pin is not used. 10.7.2 PARAMETER SETTING FOR THE MPX INPUT IGNITION DETECTOR There are in total 5 different coefficients. The settings of these coefficients are described below. On RESET, the nominal setting for a good performing MPX IAC detector is selected. 1998 May 19 20 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.7.3 AGC SET POINT (1 BIT) SAA7708H In case the sensitivity and feed forward factor are out of range in a certain application, the set point of the AGC can be shifted. The set point controls the sensitivity of the other IAC control parameters. See bit 11 of $0FFB (Table 25). 10.7.4 THRESHOLD SENSITIVITY OFFSET (3 BITS) With this parameter the threshold sensitivity of the comparator in the interfering pulse detectors can be set. It also influences the amount of unwanted triggering. Settings are according Table 31. 10.7.5 DEVIATION FEED FORWARD FACTOR (3 BITS) This parameter determines the reduction of the sensitivity of the detector by the absolute value of the MPX signal. This mechanism prevents the detector from unwanted triggering at noise with modulation peaks. In Table 32 the possible values are given. 10.7.6 SUPPRESION STRETCH TIME (3 BITS) This parameter sets the duration of the pulse suppression after the detector has stopped sending a trigger pulse. It can be switched off by applying the value 0. The duration can be selected in steps of one period of the 304 kHz (3.3 s) sample frequency. In Table 33 the possible values are given. 10.7.7 MPX DELAY With this parameter the delay time between 2 and 5 samples of the 304 kHz sample frequency can be selected. The needed value depends on the used front end of the car radio. Settings are according Table 34. 10.7.8 LEVEL IAC THRESHOLD (4 BITS) With this parameter the sensitivity of the comparator in the ignition interference pulse detector can be set. It also influences the amount of unwanted triggering. The possible values are given in Table 26. The prefix value `0000' switches the Level IAC function off. 10.7.9 LEVEL IAC FEED FORWARD SETTING (2 BITS) This parameter allows to adjust for delay differences in the signal paths from the FM antenna to the MPX mute, namely, via the FM level ADC and level IAC detection and via the FM demodulator and MPX conversion and filtering. These differences depend on the front end used in the car radio. With a simultaneous appearance of a peak disturbance at the LEVEL input and the MPX ADC input of the chip, a zero delay setting will make for the level IAC mute pulse to coincide with the passage of the disturbance in the MPX mute circuit. The setting for the Level IAC Feed Forward allows to advance the mute pulse by 1 sample period or to delay it by 1 or 2 sample periods of the 304 kHz clock, with respect to the default. The appropriate I2C bits for each setting are given in Table 27. 10.7.10 LEVEL IAC SUPPRESSION STRETCH TIME (2 BITS) This parameter sets the time the mute pulse is stretched when the LEVEL input has stopped exceeding the threshold. The duration can be selected in steps of one period of the 304 kHz (3.3 s) sample frequency. In Table 28 the possible values are given 10.7.11 DYNAMIC IAC THRESHOLD LEVELS If enabled by the lev_en_dyn_iac I2C bit (bit 15, register $0FFC) this block will disable temporarily all IAC action if the MPX mono signal exceeds a threshold deviation (threshold 1) for a given time with a given excess amount (threshold 2). This MPX mono signal is separated from the MPX signal with a low-pass filter with the - 3 dB corner point at 15 kHz. The possible values of the this threshold can be found in Table 29. 1998 May 19 21 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.7.12 IAC TESTING SAA7708H The internal IAC trigger signal is visible on DSP-OUT2 pin if the IAC_trigger bit of the IAC control register is set. In this mode the effect of the parameter settings on the IAC performance can be verified. 10.8 10.8.1 Analog outputs D/A CONVERTERS Each of the two low noise high dynamic range D/A convertors consists of a 15 bit signed magnitude DAC with current output. This DAC current is split in two parts by means of a fader. Each part of the current is fed to an operational amplifier, which converts the current into an output voltage. The fader makes it possible to make 4 outputs with only two DACS. 10.8.2 UPSAMPLE FILTER To reduce spectral components above the audio band, a fixed 4 times oversampling and interpolating 18 bits digital IIR filter is used. It is realised as a bit serial design and consists of two consecutive filters. The data path in these filters is 22 bits to prevent overflow and to maintain a theoretical SNR above 105 dB. The word clock for the upsample filter (4*asf) is derived from the audio source timing. If the internal audio source is selected, the sample frequency can be either 44.1 kHz or 38 kHz. In case of external digital sources (CD1, SPDIF), a sample frequency from 32 kHz to 48 kHz is possible. 10.8.3 VOLUME CONTROL THD+N (dB) -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 Output Level (dB) 0.0 Fig. 7 Typical THD+N curve versus output level The total volume control has a dynamic range of more than 100 dB. With the signed magnitude noise shaped 15 bit DAC and the internal 18 bits registers of the DSP core a useful digital volume control range of 100 dB is possible by calculating 1998 May 19 22 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H the corresponding coefficients. The step size is freely programmable and an additional analog volume control is not needed in this design. The SNR of the audio output at full scale is determined by the total 15 bits of the converter. The noise at low outputs is fully determined by the noise performance of the DAC. Since it is a signed magnitude type, the noise at digital silence is also low. As disadvantage the total THD is slightly higher than conventional D/A converters. The typical Signal to Noise and THD versus output level are shown in Fig. 7. 10.8.4 FUNCTION OF THE POM PIN With the POM pin it is possible to switch off the reference current source of the D/A converter. The capacitor on the POM pin determines the time after which this current has a soft switch-on. So at power-on the current audio signal outputs are always muted. The loading of the external capacitor is done in two stages via two different current sources. The loading starts at a current level that is 9 times lower than the current loading after the POM pin voltage has past the 1 V level. This results in an almost dB linear behaviour. However the DAC has an a-symmetrical supply and the DC output voltage will be half the supply voltage under functional conditions. During startup the output voltage is not defined as long as the supply voltage is lower than the threshold voltages of the transistors and a small jump in DC is possible at startup. In this DC voltage jump audio components can be present. 10.8.5 THE FADER The fader is a 5 bit I2C (bits 11-15 of $0FFC) controlled volume regulator between the front and the rear outputs. Of the 32 positions of the 5 bit I2C code position 15 is the default position in which front and rear output have the same volume (Fig. 8). Increasing the 5 bits I2C code will keep the front channels at the same volume but will decrease the volume of the rear channels. Decreasing the 5 bits code starting at position 15 will keep the rear channels at the same volume but will decrease the volume of the front channels. Starting at the default position the first 12 steps decrease the volume linearly to -26 dB, step 13 and 14 decrease until -37 dB. The positions 0 and 30 of the fader represent mute for the frontand rear channel respectively. Position 31 is not used. dB 0.0 Fader output suppression of Front and Rear channel -5.0 -10.0 -15.0 -20.0 -25.0 -30.0 Front channel -35.0 Rear channel -40.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Position of the 5 bits I2C fader code Fig. 8 DAC fader control range 1998 May 19 23 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.8.6 POWER OFF PLOP SUPPRESSION SAA7708H To reduce the chance of plops in a power amplifier, the supply voltage of the analog part of the D/A converter can be fed from the 5V via a transistor. An capacitor is connected to the 3.3 V to provide still power to the analog part the moment the digital is switching off fast. In this case the output voltage will decrease gradually allowing the power amplifier some extra time to switch off without audible plops. 10.8.7 THE INTERNAL VREFDA PIN With two internal resistors half the supply voltage VDDA2 is obtained and coupled to an internal buffer. This reference voltage is used as DC voltage for the output operational amplifiers and as reference for the DAC. In order to obtain the lowest noise and to have the best ripple rejection, a filter capacitor has to be added between this pin and ground. 10.8.8 SUPPLY OF THE ANALOG OUTPUTS All the analog circuitry of the DACs and the OPAMPS are fed by 2 supply pins, VDDA2 and VSSA2. The VDDA2 must have sufficient decoupling to prevent THD degradation and to ensure a good Power Supply Rejection Ratio. The digital part of the DAC is fully supplied from the chip core supply. 10.9 Clock circuit and oscillator The chip has an on board crystal clock oscillator. The block schematic of this Pierce oscillator is shown in Fig. 9. The active element needed to compensate for the loss resistance of the crystal is the block Gm. This block is placed between the external pins OSC_IN and OSC_OUT. The gain of the oscillator is internally controlled by the AGC block. A sine-wave with peak to peak voltage close to the oscillator power supply voltage is generated. The AGC block prevents clipping of the sine-wave and therefore the higher harmonics are as low as possible. At the same time the voltage of the sine wave is as high as possible which reduces the jitter going from sine wave to clock signal. AGC Gm CLOCK_TO_CIRCUIT Rbias ON CHIP OFF CHIP OSC_IN OSC_OUT VDD_OSC VSS_OSC Cx1 Cx2 Fig. 9 Block diagram oscillator circuit 1998 May 19 24 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.9.1 SUPPLY OF THE X-TAL OSCILLATOR SAA7708H The power supply connections of the oscillator are separate from the other supply lines. This to minimize the feedback from the ground bounce of the chip to the oscillator circuit. The VSS_OSC pin is used as ground supply and the VDD_OSC as positive supply. 10.10 The phase lock loop circuit to generate the DSP and other clocks There are several reasons why two PLL circuits to generate the DSP clock and other clocks are used: * PLL1 is used to deliver the clock to the DSP core. The deviding factor of this PLL can be changed with I2C bits PLL_DIV(3,2,1,0) but should only be used in the default position to ensure maximum functionality. * Crystals for the crystal oscillator in the range of twice the required DSP clock frequency, so approximately 45 MHz, are always third overtone crystals and must also be fabricated on customer demand. This makes these crystals expensive. The PLL2 enables the use of a crystal running in the fundamental mode and also a general available crystal can be chosen. For this circuit a 256 X 44.1 kHz = 11.2896 MHz crystal is chosen. The clock of this PLL2 is used via a sample rate converter for the AD decimation paths and stereo decoding, the SPDIF logic, the uProcessor interface and the Fader DAC upsample filters. With the I2C bit dsp_turbo (bit 11 of $0FFD) the output frequency can be doubled for test purposes by switching this bit to 1, in functional mode only the default `0' position is allowed. 10.11 The DSP core For this chip a type of DSP core (the actual programmable embedded calculating machine) is used that is adapted to the required calculation power needed and as such is optimized on area. This DSP core is also known under the name EPICS6, of which EPICS is the generic name of this type of DSP and 6 is the version number. This DSP is mainly a calculator designed for real time processing of the digitized (at 38 or 44.1 kHz sample frequency) audio data stream. A DSP is especially suited to calculate the sum of products of the digital datawords representing the audio data. 10.12 DSP core status register and the external control pins In the DSP core there is a 9 bit long status register. These 9 flags contain information which is used by the conditional branch logic of the DSP core. For direct use with the external world 4 flags are defined, F0, F1, F2 and F3. For external control two input pins, DSP_IN1 and DSP_IN2, have been implemented. These pins control the status of the flags F0 and F1. The two status flags F3 and F4 are controlled by the DSP core and can be read via the output pins DSP_OUT1 and DSP_OUT2. The functions of each pin depends on the DSP program. Another important flag is the I-flag. This flag is an input flag and is set the moment new I2S data or another type of digital audio data is available to the DSP core. 10.13 I2C control (SCL and SDA pin) General description of the I2C format in a booklet can be obtained at Philips Semiconductors, International Marketing and Sales. For the external control of the CDSP chip a fast I2C bus is implemented. This is a 400 kHz bus which is downward compatible with the standard 100 kHz bus. There are three different types of control instructions: * Instructions to control the DSP program, programming the coefficient RAM and reading the values of parameters. (level, multipath etc.) * Instructions controlling the DATA I2S flow, like source selection, IAC control and clock speed The detailed description of the I2C bus and the description of the different bits in the memory map is given in paragraph: I2C Bus control and commands. 1998 May 19 25 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.14 I2S and SPDIF inputs 10.14.1 GENERAL DESCRIPTION I2S INPUTS SAA7708H For communication with external digital sources a I2S digital interface bus can be used. It is a serial 3-line bus, having one line for data, one line for clock and one line for the word select. For external digital sources the SAA7708 acts as a slave, so the external source is master and supplies the clock. The digital audio input is capable of handling multiple input formats. For brevity the serial digital audio in- and outputs are called I2S. However this does not mean that the format is always the Philips I2S standard. The I2S input is capable of handling Philips I2S, and LSB justified formats of 16, 18 and 20 bits word sizes, fs can vary from 32 kHz until 48 kHz. See the I2C Memory Map for the bits that must be programmed, for selection of the desired I2S format. See Fig. 10 for the general waveform formats of the four possible formats. The number of bitclock (BCK) pulses may vary in the application. When the applied wordlength is smaller than 18 bits (internal resolution), the LSB bits will get internally a zero value. When the applied wordlength exceeds 18 bits, the LSB's are skipped. The input circuitry is limited in handling the number of BCK pulses per WS period. The maximum allowed number of bitclocks per WS period is 512. 10.14.2 THE TIMING DIAGRAM OF THE COMMUNICATION IS SHOWN IN FIG. 11. The DSP program is synchronised with the external source via the word select signal. On every negative edge of the IIS_WS the I flag of the status register is set. 1998 May 19 26 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.14.3 DIGITAL DATA STREAM FORMATS SAA7708H Fig. 10 All serial data in/output formats 1998 May 19 27 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H Fig. 11 Input timing digital audio data inputs Table 4 Timing digital audio inputs/out (see Fig. 11) PARAMETER rise time fall time bitclock cycle time bitclock time HIGH bitclock time LOW data setup time data hold time wordselect setup time wordselect hold time tcy=50 nS tcy=50 nS tcy=50 nS tcy=50 nS tcy=50 nS tcy=50 nS CONDITIONS tcy=50 nS tcy=50 nS 50 0.35*tcy 0.35*tcy 0.2*tcy 0.2*tcy 0.2*tcy 0.2*tcy MIN. TYP. MAX. 0.15*tcy 0.15*tcy ns ns ns ns ns ns ns ns ns UNIT NO 9.01 9.02 9.03 9.04 9.05 9.06 9.07 9.1 9.11 SYMBOL tr tf tcy tBCK(H) tBCK(L) ts;DAT th;DAT ts;WS th;WS 1998 May 19 28 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.14.4 GENERAL DESCRIPTION SPDIF INPUTS SAA7708H For communication with external digital sources also a SPDIF input can be used. The two SPDIF input pins can be connected via an analog multiplexer to the SPDIF receiver. It is a receiver without an analogue PLL that samples the incoming SPDIF with a high frequency. In this way the data is recovered synchronously on the applied system clock. Also a 64*Fs clock is regenerated out of the SPDIF datastream. From the SPDIF signal a three wire (I2S like) serial bus is made, consisting of a Wordselect, Data and Bitclock line. The FS frequency depends solely on the SPDIF signal input accuracy. This design does NOT handle the userdata-, channelstatus- and validitybits of the SPDIF stream, but only the audio is given at its outputs. The bits in the audio space are always decoded regardless of any statusbits e.g. 'copy protected', 'professional mode' or 'data mode'. 10.14.4.1 SPDIF format The SPDIF format used here carries the 2 channel PCM audio over a two wire pair. The SPDIF format can be partitioned into two main layers, being the abstract model of frames and blocks, and the channel modulation. Currently there are three samples frequencies specified: Table 5 Sample Frequencies DATA-RATE [MBIT/S] 2.8224 3.072 2.048 CHANNEL-RATE [MBIT/S] 5.6448 6.144 4.096 SAMPLE FREQ [KHZ] 44.1 48.0 32.0 10.14.4.2 SPDIF channel modulation The digital signal is coded using "biphase-mark-code" (BMC), which is a kind of phase-modulation. In this scheme, a logic one in the data corresponds to two zero-crossings in the coded signal, and a logic zero to one zero-crossing Clock Data BMC Fig. 12 BiPhase Mark Coding The SPDIF interface of the SAA7708 is capable of decoding all standardized sampling frequencies with Level3 timing being the whole range of 28 kHz to 54 kHz sampling frequency. However the highest frequency posible is in fact due to the limited cycle budget of the DSP only 44.1 kHz. 1998 May 19 29 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.14.4.3 Timing Characteristicse logic. SAA7708H The SPDIF specification IEC 958, supports three levels of clock accuracy, being high-accuracy, normal accuracy and variable or pitch shifter clock mode. * Level 1, high accuracy, tolerance of transmitting sampling frequency shall be within +50x10-6 * Level 2, normal accuracy, all receivers should receive a signal of +1000x10-6 of nominal sampling frequency * Level 3, variable pitch shifted clock mode, adeviation of 12.5% of the nominal sampling frequency is possible Rise and fall times are defined as: Rise time = 100 x R(r) / (T(l)+T(h))% Fall time = 100 x R(f) / (T(l)+T(h))% Rise and fall times should be in the range: 0%-20%when the data bit is a "1" 0%-10%when the data bits are two succeeding T(h) 90% 50% 10% T(r) T(f) T(l) Fig. 13 Rise and fall times Duty cycle shall be calculated using the equation: Duty cycle = 100 x T(h) / (T(l)+T(h))% Duty cycle shall be in the range: 40%-60% when the data bit is a logical "1" 45%-55% when the data bits are two succeeding "0"'s 10.15 RDS decoder (RDS_CLOCK / RDS_DATA pins) The RDS decoder recovers the additional inaudible RDS information which is transmitted by FM radio broadcasting. The (buffered) data is provided as output for further processing by a suitable decoder. The operational functions of the decoder are in accordance with the EBU specification EN 50067. The RDS decoder has three different functions: 1998 May 19 30 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor * Clock and data recovery from the MPX signal * Buffering of 16 bits if selected * Interfacing with the micro controller 10.15.1 CLOCK AND DATA RECOVERY The RDS-chain has a separate input FM_RDS. This enables RDS updates during tape play. SAA7708H The RDS chain contains a third order sigma-delta AD convertor, followed by two decimation filters. The first filter passes the multiplex band including the signals around 57 kHz and reduces the sigma- delta noise. The second filter reduces the RDS bandwidth around 57 kHz. The quadrature mixer converts the RDS band to the frequency spectrum around 0 Hz and contains the appropriate Q/I signal filters. The final decoder recovers the clock and data signals. These signals are output on the RDS-Clock and Data pins. 10.15.2 TIMING OF CLOCK AND DATA SIGNALS The timing of the Clock and Data output is derived from the incoming data signal. Under stable conditions the data will remain valid for 400 s after the clock transition. The timing of the data change is 100 s before a positive clock change. This timing is suited for positive as well as negative triggered interrupts on a microprocessor. The RDS timing is shown in Fig. 14. During poor reception it is possible that faults in phase occur, then the duty cycle of the clock and data signals will vary from minimum 0.5 times to a maximum of 1.5 times the standard clock periods. Normally, faults in phase do not occur on a cyclic basis. RDS_DATA RDS_CLOCK Tsr Tpr Thr Tlr Tdr Fig. 14 RDS timing in the direct output mode 10.15.3 BUFFERING OF RDS DATA The repetition of the RDS data is around the 1187 Hz. This results in an interrupt on the microprocessor for every 842 uS. In a second mode, the RDS interface has a double 16 bit buffer. 1998 May 19 31 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 10.15.4 BUFFER INTERFACE SAA7708H The RDS interface buffers 16 data bits. Every time 16 bits are received, the data line in pulled down and the buffer is overwritten. The control microprocessor has to monitor the data line in at most every 13.5 msec. This mode is selected by setting the rds_clkin I2C bit of the IIC_RDS_ConTrol register ($0FF3) (see Table 29) to "1". In Fig. 15 the interface signals from the RDS decoder and the microcomputer in buffer mode are shown. When the buffer is filled with 16 bit the data line is pulled down. The data line will remain low until reading of the buffer is started by pulling down the clock line. The first bit is clocked out. After 16 clock pulses the reading of the buffer is ready and the data line is set high until the buffer is filled again. The microprocessor stops communication by pulling the line high. The data is written out just after the clock high-low transition. The data is valid when the clock is high. When a new 16 bit buffer is filled before the other buffer is read, that buffer will be overwritten and the old data is lost. RDS_DATA D0 D1 D2 D13 D14 D15 RDS_CLOCK Twb Thb Tpb Block ready Tlb Start reading data Fig. 15 Interface signals RDS decoder and microcomputer 10.16 DSP Reset The reset pin is active low and has an internal pull-up resistor. Between this pin and the VDDD ground a capacitor should be connected to allow a proper switch on of the supply voltage. The capacitor value is such that the chip is in reset as long as the power supply is not stabilised. A more or less fixed relationship between the DSP reset (pin) and the POM (pin) time constant is obligatory. The voltage on the POM pin determines the current flowing in the DACs. At 0 V at the POM pin the DAC currents are zero and so also the DACs output voltages. At the VDDA2 voltage the DAC currents are at their nominal (maximal) value. Long before the DAC outputs get to their nominal output voltages, the DSP must be in working mode to reset the output register therefore the DSP time constant must be shorter than the POM time constant. For advised capacitors see the application diagram. The reset has the following function: * the bits of the IAC control register are set to their prefix values * the bits of the IIC_SEL register are set to their prefix values * the DSP status registers are reset * the program counter is set to address $0000. 1998 May 19 32 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor * the two output flags pin 40 and pin 41 are reset to 0 When the level on the reset pin is at logical high, the DSP program starts to run. 10.17 Power supply connection and EMC SAA7708H The digital part of the chip has in total 7 positive supply line connections and 7 ground connections. To minimise radiation the chip should be put on a double layer pcb with on one side a large ground plane. The ground supply lines should have a short connection to this ground plane. A coil/capacitor network in the positive supply line can be used as high frequency filter. 1998 May 19 33 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 11 ELECTRICAL CHARACTERISTICS LIMITING VALUES in accordance with the Absolute Maximum Ratings system (IEC 134). SYMBOL VDD3 VDD5 PARAMETER DC supply voltage DC supply voltage Only valid for the voltages in connection with the 5 V I/O's CONDITIONS MIN -0.5 -0.5 5 6 MAX V V SAA7708H UNIT DELVDD +/-Iik +/-Iok +/-Io +/-Idd +/-Iss Tamb Tstg ESDV Voltage difference between two VDDx pins DC input clamp diode current DC output clamp diode current output type 4 mA DC output source or sink current output type 4 mA DC VDD or VSS current per supply pin Ambient operating temperature Storage temperature range ESD sensitivity human body model machine model 100 pF,1500 100 pF,2.5 H, 0 CIC spec/test method 3000 300 100 Vi<-0.5 V or Vi>VDD+0.5 V Vo<-0.5 V or Vo>VDD+0.5 V -0.5 V< Vo mV mA mA mA mA C C V V mA LTCH P Ptot Latch up protection Power dissipation per output Total power dissipation 100 1600 mW mW 12 THERMAL RESISTANCE SYMBOL Rth j-a-pcb 45 PARAMETER THERMAL RESISTANCE K/W 1998 May 19 34 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 13 DC CHARACTERISTICS digital I/O at Tamb=-40oC~+85 oC,Vd5=4.5~5.5 V, Vd3=3~3.6 V unless otherwise noted SYMBOL Vd3 PARAMETER Operating supply voltage 3.3 Volt analog and digital Operating supply voltage 5 Volt periphery DC supply current of the 3.3 digital core part DC supply current of the 5V digital periphery part DC supply current of the analog part Total power dissipation At zero input and output signal high activity of the DSP at 31 MHz DSP frequency Pin types: IBUFU, BT4CR,BD4CR,B4CR, SCHMITCD,SCHMITC Pin types: IBUFU, BT4CR,BD4CR,B4CR, SCHMITCD,SCHMITC Pin type: SCHMITCD,SCHMITC CONDITIONS All VDD pins of the type VDD3 and VDDCO with respect to Vss all parts All VDD pins of the type VDD5 with respect to Vss all parts high activity of the DSP at 31 MHz DSP frequency 3 MIN TYP 3.3 MAX 3.6 SAA7708H UNIT V NO 1.01 Vd5 4.5 5 5.5 V 1.02 IP3 - 57.4 78 mA 1.03 IP5 - 5 7 mA 1.04 IPA Ptot - 17.3 0.273 23.6 0.423 mA W 1.05 1.06 VIH High level input voltage all digital inputs and I/O's Low level input voltage all digital inputs and I/O's Schmitt trigger hysteresis 70 - - %Vd5 1.07 VIL - - 30 %Vd5 1.08 Vhyst VOH VOL 1 1.3 0.4 V V V 1.09 1.10 1.11 High level output voltage Io=-4 mA, pin types: digital outputs B4CR, BD4CR,BT4CR Low level output voltage digital outputs Low level output voltage digital I2C data output Output leakage current tristate outputs Internal pull up resistor to VDDD Internal pull down resistor to VSSD Input rise and fall times Minimal output rise time VDD=4.5 V, Io=4 mA, pin types: B4CR, BD4CR,BT4CR Io=8 mA, pin types: BD4SCI4 Vout=0 or VDD voltage Pin types: BD4CR, BD4SCI4,BT4CR Pin type: IBUFU Pin type: SCHMITCD Vd5=5.5 V Vd5=5.5 V, Vd3=3.6 V, Tchip= -40 oC, pintype= BD4CR, BT4CR, B4CR, Cload = 30 pF Vd5-0.4 - VOLI2C +/-Io - - 0.4 5 V A 1.12 1.13 R_pull up R_pull down tri,tfi tro_min 23 23 7.6 50 50 6 - 80 80 200 18.4 k k ns ns 1.14 1.15 1.16 1.17 1998 May 19 35 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H SYMBOL tro_max PARAMETER CONDITIONS MIN 13.7 - TYP MAX 33.4 UNIT ns NO 1.19 Maximal output rise time Vd5=4.5 V, Vd3=3 V, Tchip= 125 oC, pintype= BD4CR, BT4CR, B4CR, Cload = 30 pF Minimal output fall time Vd5=5.5 V, Vd3=3.6 V, Tchip= -40 oC, pintype= BD4CR, BT4CR, B4CR, Cload = 30 pF Vd5=5.5 V, Vd3=3.6 V, Tchip= -40 oC, pintype= BD4SCI4, Cload = 400 pF, Rpull-up = 550 Vd5=5.5 V, Vd3=3.6 V, Tchip= -40 oC, pintype= BD4SCI4, Cload = 10 pF, Rpull-up = 550 tfo_min 7 - 17 ns 1.21 Minimal time between 1.5 and 3 V 63 - - ns 1.22 21 - - ns 1.225 tfo_max Maximal output fall time Vd5=4.5 V, Vd3=3 V, Tchip= 125 oC, pintype= BD4CR, BT4CR, B4CR,Cload = 30 pF Vd5=4.5 V, Vd3=3 V, Tchip= 125 oC, pintype= BD4SCI4, Cload = 400 pF, Rpull-up = 550 Vd5=4.5 V, Vd3=3 V, Tchip= 125 oC, pintype= BD4SCI4, Cload = 10 pF, Rpull-up = 550 12.7 - 30.9 ns 1.23 Maximal time between 1.5 and 3 V - - 197 ns 1.24 - - 184 ns 1.245 1998 May 19 36 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 14 ANALOG INPUTS Table 6 DC characteristics SAA7708H DC characteristics analog inputs at Tamb=25 oC; VDDA1=3.3 V unless otherwise noted SYMBOL VDDA1 VREFAD PARAMETER Supply voltage analog part ADC common mode w.r.t. VDDA1/VSSA1 reference voltage SCAD1, 2 and Level AD Output impedance VREFAD Positive reference voltage SCAD1, SCAD2 and Level AD Positive reference current SCAD1, SCAD2 and Level AD Negative reference voltage SCAD1, SCAD2 and Level AD Negative reference current SCAD1 and 2 Input offset voltage SCAD1 and 2 CONDITIONS 3 47 MIN TYP 3.3 50 MAX 3.6 53 UNIT V %VDD A1 ohm V NO 2.01 2.02 ZOUT VDACP 3 600 3.3 3.6 2.03 2.04 IVDACP - -20 - A 2.05 VDACN1 VDACN2 IVDACN1 IVDACN2 AVO_SCAD -0.3 0 0.3 V 2.06 - 20 - A mV 2.07 - +140 - 2.09 Table 7 AC characteristics AC characteristics analog level inputs at VDDA1=3.3 V; Tamb=25 oC SYMBOL ADSNR ADIRES ADICL ADOS ADDEC ADPCOF ADSF PARAMETER CONDITIONS MIN 48 1.5 0 20 at - 3 dB and DCS clock = 9.728 MHz DCS clock = 9.728 MHz 29 38 TYP 54 2.2 VDDA1 60 MAX UNIT dB M V mV dB/Dec kHz kHz NO 3.01 3.02 3.03 3.04 3.05 3.06 3.07 Level AD converter SNR BW=0-29 kHz Max. RMS (unweighted) input Input resistance Input voltage range level AD for full scale DC-offset voltage decimation filter attenuation pass band cutoff freq. sample rate after decimation 1998 May 19 37 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor Table 8 Analog AC inputs: SAA7708H Analog AC inputs SCAD1,2, VDDA1=3.3 V; Tamb=25 oC SYMBOL AILVL AIIRG AIIRM AITHDM PARAMETER maximum conversion input level at AD input input resistance AM, CD, TAPE input resistance FM_MPX THD FM_MPX input 1 kHz 1.1 Vrms, BW= 19 kHz, I2C default setting CONDITIONS THD < 1% MIN 0.6 1 31 TYP 0.66 45 -70 0.03 60 -65 0.056 MAX UNIT Vrms M k dB % NO 3.08 3.09 3.10 3.11 AISNRM SNR FM_MPX input mono 1 kHz, BW=19 kHz, 0 dB ref. = 1.1 Vrms, I2C default setting SNR FM_MPX input stereo 1 kHz, BW=40 kHz, 0 dB ref. = 1.1 Vrms, I2C default setting THD CD Inputs not multiplex mode SNR CD Inputs not multiplex mode 1 kHz, 0.55 Vrms, BW=20 kHz 80 83 - dB 3.12 AISNRSS 74 77 - dB 3.13 AITHDC - -80 0.01 84 -76 0.016 - dB % dB 3.14 AISNRC 1 kHz, 81 BW=20 kHz, 0 dB ref.= 0.55 Vrms 1 kHz, 0.55 Vrms, BW=5 kHz - 3.15 AITHDA THD AM mono input, not multiplex mode SNR AM mono input, not multiplex mode THD Tape input, multiplex mode SNR Tape input, multiplex mode -80 0.01 88 -76 0.016 - dB % dB 3.16 AISNRA 1 kHz, BW=5 83 kHz, 0dB ref. = 0.55 Vrms 1 kHz, BW = 20 kHz, 0.55 Vrms 1 kHz, BW= 20 kHz, 0 dB ref. = 0.55 Vrms - 3.17 AITHDT -80 0.01 -76 0.016 - dB % dB 3.18 AISNRT 70 77 3.19 1998 May 19 38 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H SYMBOL a19 PARAMETER Carrier and harmonic suppression at the output with and without modulation CONDITIONS pilot sig. f=19 kHz no mod subcarrier f=38 kHz no mod subcarrier f=57 kHz no mod subcarrier f=76 kHz no mod - MIN TYP 81 98 83 91 83 96 84 94 110 110 110 110 22.2 22.1 0 - MAX UNIT dB dB dB dB dB dB dB dB dB dB dB dB dB dB mVrms mVrms dB kHz NO 3.21 3.22 3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.36 3.37 3.38 a38 a57 (for 19 kHz, incl. notch (See note 1) a76 a2 a3 a57VF a67 a114 a190 Vi-pil H AIFR Intermodulation (see note 2) fmod=10kHz,f spur=1kHz fmod=13kHz,f spur=1kHz 77 76 0 Traffic radio (see note 3) SCA (note 4) Adjacent channel interference (note 5) pilot threshold voltage (pin 40) hysteresis of Vi-pil input freq. range MPX f=57 kHz f=67 kHz f=114 kHz f=190 kHz stereo on stereo off -3 dB, AD via bitstream test output 1 kHz 10 kHz at -3 dB via DSP at DAC output Multiplex mode, 1 kHz, SW compensated Not multiplexed, 1 kHz 1 kHz, SW compensated at -3 dB 1 kHz 15 kHz 55 AISEP FM-stereo channel separation 40 25 17 45 30 - - dB dB kHz 3.39 3.40 3.41 AIAFR Audio freq. response FM AIOGV overall gain unbalance Left/Right TAPE, CD, AM - - 2 dB 3.42 AIOGVNM overall gain unbalance Left/Right TAPE, CD, AM Channel separ. TAPE, CD Freq. response TAPE, CD for fs=38 kHz Crosstalk between inputs - - 0.5 dB 3.425 AICST AIFRT AICRI 40 18 65 50 50 - - dB kHz dB dB 3.43 3.46 3.47 3.48 1998 May 19 39 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H SYMBOL PSRRAD PARAMETER Power Supply Ripple Rejection MPX and RDS ADCs (output via I2S), ADC input shorted CONDITIONS Fripple = 1 kHz Vripple = 100 mVpeak; Cvrefad = 22 F; Cvdacpm = 10 F; Fripple = 1 kHz Vripple = 100 mVpeak; Cvrefad = 22 F; R CD_GND = 1 M, R CD Player GND cable < 1k Fin= 1 kHz MIN 35 TYP 45 - MAX UNIT dB NO 3.49 PSRRLD Power Supply Ripple Rejection Level AD (output via DAC) ADC input shorted Common Mode Rejection Ratio in CD input mode 29 39 - dB 3.50 CMRRCD 60 - - dB 3.51 PHONE_THD THD Phone input at max. input voltage Vin=0.75 Vrms, F=1 kHz 40 - - dB 3.52 PHONE_CMRR Common mode rejection ratio phone input Vin=0.75 Vrms, F=1 kHz 50 - - dB 3.53 PHONE_RIN PHONE_IPLEV Input resistance phone input Maximum input level F=1 kHz 0.75 Vrms - k V 3.54 3.55 Table 9 Analog AC input SCAD2 RDS input SYMBOL ARLVL ARIR ARTHD ARSNR PARAMETER maximum conversion input level Input resistance FM_RDS Distortion RDS AD Signal to noise ratio RDS AD Pilot attenuation RDS Nearby selectivity RDS fc = 57 kHz CONDITIONS THD < 1% MIN 0.6 31 -60 BW = 6 kHz, fc 54 = 57 kHz, 0 dB ref. = 1.1 Vrms 50 neighbour 61 channel at 200 kHz distance 70 TYP 0.66 -67 164 MAX UNIT Vrms k dB dB NO 4.01 4.02 4.03 4.04 ARPA ARNS - - dB dB 4.05 4.06 ARNA RDS AD converter noise attenuation dB 4.07 1998 May 19 40 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H SYMBOL ARPR ARMA ARAFD PARAMETER Pass band ripple RDS Multiplex attenuation RDS Allowable frequency deviation 57 kHz RDS CONDITIONS 2.4 kHz BW mono stereo Max Crystal deviation of 100 ppm - MIN 70 40 - TYP 6 MAX 0.5 UNIT dB dB dB Hz NO 4.08 4.09 4.10 4.11 Table 10 Analog SPDIF SPDIF input 1 and 2 SYMBOL SPVL SPIR SPHYS PARAMETER AC input level Input resistance Hysteresis of input @ 1 kHz CONDITIONS MIN 0.2 6 40 TYP 0.5 MAX 3.3 UNIT Vpp k mV NO 11.01 11.02 11.03 15 ANALOG OUTPUTS Table 11 DC characteristics analog outputs at Tamb= 25 oC; VDDA2= 3.3 V unless otherwise noted. SYMBOL VREFDA IMPP_VREF PARAMETER Voltage on VREFDA pin Impedance VREFDA to VDDA2 pin Impedance VREFDA to VSSA2 pin Output voltage AC Rload > 5 k AC of Op-Amp outputs at max. I2S signal Average DC output voltage Pull-up current to VDDA2 on POM pin Pull-up current to VDDA2 on POM pin Power Supply Ripple Rejection DACs (input via I2S) Rload > 5 k AC CONDITIONS w.r.t. VDDA2/VSSA2 MIN 47 TYP 50 40 MAX 53 UNIT % k NO 5.01 5.02 IMPG-VREF - 40 - k 5.03 VOUT_AC 0.65 0.75 0.85 Vrms 5.05 VOUT_DC 1.5 1.65 1.8 V A 5.06 I_POML Voltage on POM pin 3.3 < 0.6 V Voltage on POM pin 50 > 0.8 V Fripple = 1 kHz Vripple = 100 mVpeak Cvref = 22 F 45 - 5 5.073 I_POMH - 75 A 5.076 PSRRDA 60 - dB 5.08 1998 May 19 41 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H SYMBOL UNBAL PARAMETER max. deviation in output level (plus or minus) of the 4 DAC current outputs w.r.t. the average of the 4 outputs Crosstalk between outputs in the audio band Left or right outputs dig. silence, other max. volume Output short circuit current DAC resolution CONDITIONS Full scale output. No phone, no fader - MIN - TYP MAX 0.38 UNIT dB NO 5.085 XT - - -69 dB 5.09 ISC DAC_Rs THD&N/S Output short circuit to ground - 18 20 mA bit 5.10 5.11 5.12 Total harmonic f = 1 kHz, distortion +noise vs Vout=0.72 Vrms Output Signal Dynamic Range (ref. Vout=0.75 Vrms=0 dB) f = 1 kHz, -60 dB - -75 -65 dBA DRAN 92 102 - dBA 5.13 DSIL DSIL Digital Silence (ref. Vout=0.75 Vrms=0 dB) f=20 Hz-17 kHz A-weighted - 108 102 dBA 5.14 DSNS Digital Silence Noise level at output Intermodulation distort./comp A-weighted - 3 8 Vrms 5.15 IM f = 60 Hz and 7 kHz ratio 4: 1 48 -70 -55 dB 5.16 MASF Maximum sample frequency - - kHz 5.17 B DAC-Cload Bandwidth D/A Allowed load capacitance on DAC outputs Allowed load resistor on DAC voltage outputs at - 3 dB - Fs/2 2.5 nF 5.18 5.19 DAC-Rload Only AC coupled 5 - - k 5.20 1998 May 19 42 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 16 OSCILLATOR Table 12 Oscillator specifications SYMBOL XTFREQ PARAMETER X-tal frequency Adjustment tolerance temperature drift XSPFRAT Spurious frequency attenuation Voltage across the crystal Trans conductance (gm) Transconductan ce (gm) Load capacitance Number of cycles in start up time Supply current Supply current Drive level External clock input Allowed loss resistor of the crystal Depends on quality of the external crystal At start-up At oscillation At oscillation in slave mode Cp = 6pF, Cx1 = 18 pF, Cx2 = 18 pF. At start-up Tamb = 25 0C -30 -30 20 CONDITIONS MIN TYP 11.2896 +30 +30 MAX SAA7708H UNIT MHz ppm ppm dB NO 6.01 6.02 6.03 6.04 XVOLT XTRCUN 10.5 3 19 32 V mS 6.05 6.06 XTROSC XLOAD NRCYC In operating range 3.6 - 15 1000 38 - mS pF cycles 6.07 6.08 6.09 IP_XTAL IP_XTAL XTAL_DL XTAL_INP RXTAL 3 - 7 0.6 0.4 3.3 20 15 2 0.5 5 100 mA mA mW V 6.10 6.11 6.12 6.13 6.15 1998 May 19 43 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 17 RDS TIMING Table 13 Timing of the RDS interface (see Fig. 14and Fig. 15) SYMBOL Frdscl PARAMETER nominal clock frequency RDS clock Clock set-up time Periodic time Clock high time Clock low time Data hold time Wait time Periodic time Clock high time Clock low time input frequency Extern RDS-Clock CONDITIONS MIN TYP 1187.5 MAX SAA7708H UNIT Hz NO 8.01 Tsr Tpr Thr Tir Tdr Twb Tpb Thb Tlb Fexcl 100 220 220 100 1 2 1 1 - 842 - 640 640 22 s s s s s s s s s MHz 8.02 8.03 8.04 8.05 8.06 8.09 8.10 8.11 8.12 8.13 18 SUPPLY CURRENTS Table 14 Current per supply pin or pin group SYMBOL Vd3 PARAMETER CONDITIONS MIN 3.0 TYP 3.3 MAX 3.6 V UNIT NO 7.01 Operating supply with respect to Vss all voltage 3.3 Volt parts analog and digital Operating supply with respect to Vss all voltage 5 Volt parts periphery DC supply high activity of the DSP current of the 3.3 at 27 MHz DSP digital core part frequency DC supply current of the 5V digital periphery part Vd5 4.5 5 5.5 V 7.02 IP3 - 57.4 68 mA 7.03 IP5 Without external load to ground 5 7 mA 7.04 IPAD Supply current of At zero input and the AD's output signal - 11 15 mA 7.05 1998 May 19 44 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H SYMBOL IPDAC PARAMETER CONDITIONS - MIN TYP 4.3 MAX 5.8 UNIT mA NO 7.06 Supply current of At zero input and the DAC's and output signal SPDIF block Supply current XTAL oscillator and PLL's Total power dissipation Functional mode IP_XTAL - 2 2.75 mA 7.07 Ptot - 0.273 0.423 W 7.08 1998 May 19 45 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 19 I2C BUS CONTROL AND COMMANDS 19.1 Characteristics of the I2C Bus SAA7708H The I2C bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to the VDD via a pull-up resistor when connected to the output stages of a micro controller. For a 400 kHz I2S the recommendation for this type of bus from Philips Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a pull-up resistor can be used, between 200 400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy. 19.2 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 400 kHz. To be able to run on this high frequency all the In-Outputs connected to this bus must be designed for this high speed I2C bus according the Philips specification. See Fig. 16. S DA S CL dat a l i ne change of dat a a l l o we d st abl e; dat a val i d Fig. 16 Bit transfer on the I2C bus 19.3 Start and stop conditions Both data and clock line will remain HIGH when the bus in not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as a start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a stop condition (P). See Fig. 17. 1998 May 19 46 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H SDA SCL st ar t S condi t i on P st op condi t i on Fig. 17 START and STOP condition 19.4 Data transfer A device generating a message is a "transmitter", a device receiving a message is the "receiver". The device that controls the message is the "master" and the devices which are controlled by the master are the "slaves". See Fig. 18. SDA MSB a c k n o wl e d g e me n t si gnal f r om r ec ei v er b y t e c o mp l e t e , i n t e r r u p t wi t h i n r e c e i v e r c l o c k l i n e h e l d l o w wh i l e i nt er r upt ar e ser vi ced a c k n o wl e d g e me n t si gnal f r om r ecei SCL S st ar t condi t i on 1 2 7 8 9 ACK 1 2 3- 8 9 ACK Fig. 18 Data transfer on the I2C-bus 19.5 Acknowledge The number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. At the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA 1998 May 19 47 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Setup and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. See Fig. 19. DA T A BY OUT P UT T R A NS MI T T E R not a c k n o wl e d g e DA T A BY OUT P U T RE CE I V E R a c k n o wl e d g e S CL F R OM MA S T E R 1 S st ar t condi t i on 2 7 8 cl ock 9 pul se f or a c k n o w l e d g e me n t Fig. 19 Acknowledge on the I2C bus. 20 I2C BUS FORMAT 20.1 Addressing Before any data is transmitted on the I2C bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. 20.2 Slave address (A0 pin) The CDSP acts as slave receiver or a slave transmitter. Therefore the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The CDSP slave address is shown in table Table 15. Table 15 Slave address MSB 0 0 1 1 1 0 A0 LSB R/W The sub address bit A0 corresponds to the hardware address pin A0 which allows the device to have 2 different addresses. The A0 input is also used in test mode as serial input of the test control block. 1998 May 19 48 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 20.3 CDSP write cycles I2C SAA7708H The bus configuration for a WRITE cycle is shown in table Table 16. The write cycle is used to write the bytes to control the DCS block, the PLL for the DSP clock generation, the IAC settings, the AD volume control settings, the analog input selection, the format of the I2S and some other settings. More detail can be found in the I2C memory map, Table 19. Table 16 Master transmitter writes to the CDSP registers. A C K RN /. WC D S P S 0011100 0 A AddrH A C K N . C D S P A AddrL A C K N . C D S P A C K N . C D S P A C K N. C D S P DataL A C K N . C D S P AP A DataH A DataM A auto increment if repeated n-groups of 3 (2) bytes S P A AddrH and AddrL DataH, DataM and DataL DataH and DataM = Start condition = Stop condition = Acknowledge from CDSP = Address DSP register = Data of XRAM or registers = Data of YRAM The datalength is 2 bytes or 3 bytes depending of the accessed memory. If the Y-memory is addressed the data length is 2 bytes, in case of the X-memory the length is 3 bytes. The slave receiver detects the address and adjusts the number of bytes accordingly. 20.4 CDSP READ cycles The I2C bus configuration for a read cycle is shown in table Table 17. The read cycle is used to read the data values from XRAM or YRAM. The master starts with a start condition S, the CDSP address `0011100' and a `0' (Write) for the read/write bit. This is followed by an acknowledge by the CDSP. Then the Master writes the memory address High and memory addres Low where the reading of the memory content of the CDSP must start. The CDSP acknowledges these addresses both. Then the master generates a repeated Start (Sr) and again the CDSP address `0011100' but this time followed by a `1' (Read) of the read/write bit. From this moment on the CDSP will sent the memory content in groups of 2 (Y-memory) or 3 (X-memory) bytes to the I2C bus each time acknowledged by the Master. The Master stops this cycle by generating a Negative Acknowledge, then the CDSP frees the I2C bus and the Master can generate a Stop condition. The data is transferred from the DSP register to the I2C register at execution of the MPI instruction in the DSP program. 1998 May 19 49 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor Table 17 Master transmitter reads from the CDSP registers. A C K N . M A S T E R A C K N . M A S T E R SAA7708H A C K RN /. WC D S P S 0011100 0 A AddrH A C K N . C D S P A AddrL A C K N . C D S P A S 0011100 r A C K RN /. WC D S P A C K N . M A S T E R DataL A N A . M A S T E R 1 A DataH A DataM A N A P auto increment if repeated n-groups R of 3 (2) bytes S Sr P A R NA AddrH and AddrL DataH, DataM and DataL DataH and DataM = Start condition = repeated Start condition = Stop condition = Acknowledge from CDSP (SDA low) = Repeat n-times the 2 or 3 byte data group = Negative Acknowledge Master (SDA high) = Address DSP register = Data of XRAM or registers = Data of YRAM Table 18 Timing fast I2C-bus(see Fig. 20) SYMBOL PARAMETER CONDITIONS STANDARD MODE I2C BUS MIN. fSCL tBUF SCL clock frequency Bus free between a STOP and Start Condition Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock 0 4.7 MAX. 100 0 1.3 FAST MODE I2C BUS MIN. - MAX. 400 kHz S 10.01 10.02 UNIT NO tHD;STA 4.0 - 0.6 - S 10.03 tLOW tHIGH 4.7 4.0 - 1.3 0.6 - S S 10.04 10.05 1998 May 19 50 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H SYMBOL PARAMETER CONDITIONS STANDARD MODE I2C BUS MIN. MAX. - FAST MODE I2C BUS MIN. 0.6 MAX. UNIT NO tSU;STA Set-up time for a repeated start condition DATA hold time DATA set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Capacitive load for each bus line Pulse width of spikes to be suppressed by input filter Cb in pF Cb in pF 4.7 S 10.06 tHD;DAT tSU;DAT tr tf tSU;STO Cb tSP 0 250 4.0 n/a 1000 300 400 n/a 0 100 20 + 0.1Cb 20 + 0.1Cb 0.6 - 0.9 300 300 400 50 S nS nS nS S pF nS 10.07 10.08 10.09 10.10 10.11 10.12 10.13 0 SDA tLOW tBUF tR-IIC tF-IIC tHD;STA tSP SCL P S tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA Sr tSU;STO P Fig. 20 Definition of timing on the I2C-bus 1998 May 19 51 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H 20.5 I2C memory map specification I2C The Memory map contains all defined I2C bits. The map is split up in two different sections, hardware memory registers and the RAM definitions. In Table 19 the preliminary memory map is depicted. Table 20 shows the detailed memory map locations. Table 19 I2C memory map $8000 - $9FFF $1000 - $7FFF $0FFB - $0FFF $0A00 - $0FFA $0980 - $09FF $0800 - $097F $0200 - $07FF $0180 - $01FF $0000 - $017F Reserved Not Used EPICS6 Reserved Reserved YRAM space YRAM Not Used Reserved XRAM space XRAM 384*18 bits 384*12 bits 5 *16 bits Table 20 I2C memory map overview EPICS6 IIC_DSP_CNTR IIC_SELECTION IIC_ADDA IIC_LEVEL_IAC IIC_IAC 20.6 I2C Memory map definition #REGISTER $0FFF $0FFE $0FFD $0FFC $0FFB Table 21 IIC_DSP_CNTR register ($0FFF) NAME loopo_on_off bypass_pll PLL_div dsp_turbo pc_reset Not Used BITS 1 1 4 1 1 8 DESCRIPTION Loopo on (1) or off (0) off DEFAULT 0 1 5-2 6 7 15 - 8 BIT POS. Bypasses the PLL with the Oscillator clock signal PLL active (1) or PLL active (0) PLL clock division factor (see Table 30) Double PLL output frequency (1) Program Counter Reset (1) 176 disable no-reset - 1998 May 19 52 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor Table 22 IIC_SELECTION register ($0FFE) NAME phone_vol audio_source audio_format dac_hold sel_SPDIF adc_bw_switch locked_preset gain_h_l Not Used BITS 5 2 3 1 1 1 1 1 1 DESCRIPTION Phone volume settings according Table 2 Selection AUDIO register according Table 36 AUDIO register data format according Table 37 Hold sign magnitude data stream (1) going to DAC Select SPDIF1 (0) or SPDIF2 (1) input Switching SCAD1, SCAD2 and level_AD from 38KHz (0) to 44.1KHz (1) based processing DCS clock locked (1) or preset (0) Variable loop-gain stereo decoder high (1) or low (0) DEFAULT 1111d (mute) ISN ISN no-hold SPDIF1 38KHz locked high - SAA7708H BIT POS. 4-0 6, 5 9-7 10 11 12 13 14 15 Table 23 IIC_ADDA register ($0FFD) NAME pcs_ad_sel en_38_clk sw_ad1 s1_2 s4_5 s6_7 s8_9 rds_cd_sel rds_clk_in Not Used s10 s11 FR_b FL_b wide_narrow Not Used BITS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DESCRIPTION DEFAULT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BIT POS. Select two input sensitivities, 200 mVrms (0) or 65 200 mVrms mVrms (1) Disable 38 kHz Fs clock (0) for pseudo stereo Right (0) vs Left (1) AD channel select according Table 3 CD (0) vs Tape (1) select according Table 3 Tape/CD (0) vs AM (1) select according Table 3 AD left channel (0) vs Phone (1) select according Table 3 FM/RDS_MPX (0) vs AD right channel (1) select according Table 3 FM/RDS_MPX (0) vs AD right channel (1) select according Table 3 Select RDS output (0) or buffered RDS with RDS clock input (1) Selection switch CD_GND (0) or AUX_GND (1) pin Selection switch internal Midref-voltage reference (0) or external ground pin (1) Enable phone signal (1) to DAC front right output Enable phone signal (1) to DAC front left output Audio+RDS info (0) or audio data (1) disable Right CD TAPE/CD AD left channel FM/RDS_MPX FM/RDS_MPX RDS out CD_GND Midref disable disable audio + RDS - 1998 May 19 53 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor Table 24 IIC_LEVEL_IAC register ($0FFC) NAME lev_iac_threshold BITS 4 DESCRIPTION IAC level threshold setting (see Table 26). At `0000' Level IAC is switched off IAC level deviaton feed forward factor (see Table 27) IAC level stretch time (see Table 28) DEFAULT Level IAC on at 0.063 0 periods 13 periods SAA7708H BIT POS. 3-0 5, 4 7, 6 9, 8 10 15 - 11 lev_iac_feedforward 2 lev_iac_stretch lev_dyn_iac_dev lev_en_dyn_iac fader_vol 2 2 1 5 the deviation threshold frequency setting of the 74 kHz dynamic IAC (see Table 29) enables FM frequency sweep dependent IAC (1) 1 Fader volume regulator settings according Fig. 01111 8 in position number 15 Table 25 IIC_IAC register ($0FFB) NAME Threshold feed_forward Suppression MPX_delay AGC GDC IAC_trigger 20.7 BITS 3 3 3 2 1 3 1 DESCRIPTION Threshold sensitivity (see Table 31) Deviation feed forward factor (see Table 32) Stretch time suppression (see Table 33) Delay settings MPX (see Table 34) AGC set point 1/256 (1) or 1/128 (0) Group delay compensation (see Table 35) IAC output (1) or DSP_OUT2 output selection DEFAULT 0.031 0.01172 5 samples 5 periods 1/256 1200 ns DSP 2-0 5-3 8-6 10, 9 11 14 - 12 15 BIT POS. Table definitions Table 26 Level IAC theshold settings IIC VALUE Bit3 0 0 0 0 0 0 0 0 1 1 1 1 1 Bit2 0 0 0 0 1 1 1 1 0 0 0 0 1 Bit1 0 0 1 1 0 0 1 1 0 0 1 1 0 Bit0 0 1 0 1 0 1 0 1 0 1 0 1 0 Level IAC off 0.02 0.025 0.0316 0.04 0.05 0.063(prefix) 0.08 0.1 0.126 0.16 0.2 0.25 Level IAC off 0.0000010 0.0000011 0.0000100 0.0000101 0.0000110 0.0001000 (prefix) 0.0001010 0.0001101 0.0010000 0.0010100 0.0011010 0.0100000 THRESHOLD (DECIMAL VALUE) THRESHOLD (BINARY VALUE) 1998 May 19 54 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 1 1 1 1 1 1 0 1 1 1 0 1 0.316 0.4 0.5 0.0101000 0.0110100 0.1000000 SAA7708H Table 27 IAC level deviaton feed forward factor IIC VALUE Bit5 0 0 1 1 Bit4 0 1 0 1 -2 -1 0(prefix value) 1 DELAY (DECIMAL VALUE) IN PERIODS OF 304 KHZ Table 28 IAC level stretch time IIC VALUE Bit7 0 0 1 1 Bit6 0 1 0 1 PULSE LENGTH ON SINGLE TRIGGER IN PERIODS OF 304 KHZ 9 11 13 (prefix value) 15 Table 29 Dynamic IAC deviation threshold CODE BIT 9 0 0 1 1 0 1 0 1 BIT 8 42 48 57 70 DEVIATION VALUE KHZ 0.26 0.30 0.35 0.39(prefix) Table 30 IIC PLL division settings VALUE PLL_DIV(3) BIT 15 0 0 0 0 0 0 0 0 1 1998 May 19 0 0 0 0 1 1 1 1 0 PLL_DIV(2) BIT 14 0 0 1 1 0 0 1 1 0 PLL_DIV(1) BIT 13 0 1 0 1 0 1 0 1 0 55 PLL_DIV(0) BIT 12 93 99 106 113 121 126 132 137 143 DIVISION FACTOR N Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor SAA7708H VALUE PLL_DIV(3) BIT 15 1 1 1 1 1 1 1 0 0 0 1 1 1 1 PLL_DIV(2) BIT 14 0 1 1 0 0 1 1 PLL_DIV(1) BIT 13 1 0 1 0 1 0 1 PLL_DIV(0) BIT 12 148 154 159 165 170 176 (prefix) 181 DIVISION FACTOR N Table 31 IIC IAC Threshold settings VALUE BIT 2 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 BIT 1 0 1 0 1 0 1 0 1 BIT 0 THRESHOLD (DECIMAL VALUE) 0.027 0.031 (prefix) 0.038 0.047 0.055 0.063 0.074 0.085 THRESHOLD (BINARY VALUE) 0.000001110000 0.000010000000 0.000010011100 0.000011000000 0.000011100000 0.000100000000 0.000100110000 0.000101100000 Table 32 IIC IAC Feed forward factor settings VALUE BIT 5 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 BIT 4 1 0 1 0 1 0 1 0 BIT 3 FACTOR (DECIMAL VALUE) 0.00146 0.00195 0.00293 0.00391 0.00586 0.00781 0.01172(prefix) 0.00000 FACTOR (BINARY VALUE) 0.000000000110 0.000000001000 0.000000001100 0.000000010000 0.000000011000 0.000000100000 0.000000110000 0.000000000000 1998 May 19 56 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor Table 33 IIC IAC Suppression stretch time VALUE BIT 8 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 BIT 7 1 0 1 0 1 0 1 0 BIT 6 PULSE LENGTH ON SINGLE TRIGGER 0 1 2 3 4 5 6 7 N.A. 0 1 2 3 4 5(prefix) 6 STRETCH (# SAMPLES) SAA7708H Table 34 IIC IAC MPX Delay settings VALUE BIT 10 1 1 0 0 0 1 0 1 BIT 9 2 3 4 5 (prefix) DELAY (DECIMAL VALUE) PERIODS OF 304 KHZ Table 35 IIC group delay compensation bits BIT 14 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 BIT 13 0 1 0 1 0 1 0 1 BIT 12 8 9 10 11 12 (prefix) 13 14 15 DELAY (TIMES 100 NS) Table 36 IIC audio_source mode bits AUDIO_SOURCE(1) BIT 6 0 1 1 d 0 1 AUDIO_SOURCE(0) OUTPUT BIT 5 ISN L+R, R-L (prefix) External CD1 External SPDIF 1998 May 19 57 Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor Table 37 IIC audio_format bits AUDIO_FORMAT(2) BIT 9 0 0 1 1 0 0 1 1 0 0 AUDIO_FORMAT(0) BIT 8 0 1 0 1 0 1 AUDIO_FORMAT(0) OUTPUT BIT 7 ISN, LSB first (prefix) LSB justified, 16 bits LSB justified, 18 bits LSB justified, 20 bits Standard I2S SPD3 format SAA7708H 21 APPLICATION DIAGRAM The application diagram shown on the next page must be considered as one of the examples of a (limited) application of the chip e.g. in this case the I2S inputs of the CD1 and CD2 are not used. For the real application set-up the information of the application report and application support by Philips is necessary on issues like EMC, Rth reduction of the package, DSP program etc. 1998 May 19 58 VSSG VDDA1 DSP-IN1 VSSD3V1 VSSD3V2 VSSD3V3 VSSD3V4 VSSD5V1 VSSD5V2 VDDD5V2 VDDD5V3 VDDD3V1 VDDD3V2 VDDD3V3 DSP-OUT1 VDACN1 VSSA2 LEVEL POM + C32 4.7 F 16 + 10nF 2.2F C37 + C42 15 13 14 9 8 6 7 RRI 12 AM-AF-R VREFDA 34 TP11 TAPE-L TP12 35 TP7 TAPE-R 2 FM-MPX FM-RDS SEL-FR CD-CL CD-WS SPDIF1 SPDIF2 TP6 TP5 OSC-IN TP1 TP2 TP3 TP4 VSS-OSC CD-DATA RTCB SHTCB TSCAN VDD-OSC DSP-OUT2 R2 27k 100F 2 10 100 nF 5 22 F 3 71 PHONE PHONE_GND R27 C33 100 2.2nF R28 C34 100 2.2nF R29 C35 100 2.2nF R30 C36 100 2.2nF C41 CD-LI FLI FRV FLV 73 72 C30 C31 VSSA1 C59 R34 PHONE VDDD5V1 VDDD3V4 C1 VSSD5V3 DSP-IN2 SCL OSC-OUT SDA A0 RDS-DATA R16 43 44 17 18 60 C20 X1 10nF L1 C21 18pF C22 18pF C57 100nF 59 64 62 29 28 27 19 20 21 45 65 63 FM RDS-CLOCK 3.3k 150pF C15 R19 220 C19 100pF 25 24 26 57 58 56 DSPRESET 220 C18 100pF BLM21A10 1998 May 19 +3.3 V dig +5 V dig +5 V ana +3.3 V ana R22 C26 C27 C29 100pF 100pF 100pF R25 220 T1 R32 4.7 k 40 VDDA2 + 11 41 R26 220 C28 100pF C48 R23 22nF 22nF 220 49 38 39 50 53 54 23 37 47 48 51 52 55 R24 220 R31 1.2 k C49 100 C47 22nF C46 100nF 74 1 VDACP 76 75 22 36 46 L3 + 5V ana 100 H + 5V MICRO CONTROL + 5V dig + C51 + C52 Philips Semiconductors 100F 100nF + 3.3V ana +3.3 V R17 100 + 3.3V dig + C53 + C54 Fig. 21 Application diagram 22F 10nF R1 FM-LEVEL 27k 330pF C17 + 220nF MICRO CONTROL C60 PHONE_GND 6.8K R36 R35 100K LEVEL AD Signal Level 220nF C2 6.8K CD-L 4 AUX_GND + R3 FRONT - LEFT 2.2 F 8.2K R4 10K C55 1nF Signal Quality C56 70 CD-RI CD-GND 77 78 VREFAD Car Radio Digital Signal Processor CD-R C3 + R5 R6 10K 1nF ANALOG SCAD1 Digital Source DAC RLV RLI IAC DSP FRI Stereo decoder Quad 2.2 F 8.2K 10nF 2.2F C38 C43 + 10nF 2.2F C39 C44 + 10nF 2.2F C40 FRONT - RIGHT R7 SOURCE SELECTOR SCAD2 Selector RRV REAR - LEFT 59 R9 67 AM-AF-L R11 66 + R13 69 CD-GND C4 + 1M 1 F C5 + 22 F 47 nF C6 82k REAR - RIGHT C7 R8 AM-L 220nF 68k 82k 100pF C8 C9 R10 SAA7708H C45 22 F AM-R R15 68 80 79 61 220nF 68k 100pF C10 82k C11 C16 680nF R12 82k 30 TP10 TP8 TP9 33 31 32 TAPE-L 220nF 68k 100pF C12 RDS decoder XTAL osc IC C13 R14 TAPE-R 220nF 68k 100pF C14 42 MICRO CONTROL R20 220 C23 100pF R21 220 C24 100pF C25 220nF R18 SPDIF R33 RDS DATA CLOCK Preliminary specification SAA7708H RDS +3.3 V ana C58 75 100pF SCL SDA Philips Semiconductors Preliminary specification Car Radio Digital Signal Processor 22 MECHANICAL OUTLINE DRAWING OF PACKAGE SAA7708H y X 64 65 41 40 ZE A Fig. 22 SOT318D4 e E HE wM pin 1 index bp 25 1 wM D HD ZD B vM B 24 vMA A A2 A1 Q (A 3) q Lp L detail X 80 e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.2 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.45 0.30 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.8 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 q 7o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 92-12-15 95-02-04 1998 May 19 60 |
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